DFL-200 » History » Version 36
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Gordon Shumway, 09/18/2012 04:07 PM
This page is a work in progress and changes as the hardware is mapped out.
- Table of contents
|Ethernet controller||1||Realtek RTL8100B|
|2||IXP422 Built-in MAC|
|IDE controller||1||Promise PDC20275|
|10/100 Eth||6||1 on the RTL8100B (WAN)
1 on NPE-C connected to the switch (DMZ)
4 on NPE-B connected to the switch, PHY 32 (LAN)
|LEDs||1||GPIO-controlled Status LED (LED20)
(plus Ethernet port LEDs controlled by the switch)
|Buttons||2||GPIO, Reset button on the rear panel (RSW1), active low
Hardware reset button (RSW2) inside the case
|GPIO||4||On GPIOA1; 2 of these are the IIC bus|
|CF||1||On the IDE controller|
|RTC||1||With battery backup; on the IIC bus|
|JTAG||3||1 standard 20-pin ARM JTAG (JB1)
1 that appears to be a minimal version of a standard JTAG (JC1)
1 unknown (DEBUG2), possibly the DSP engine
|Serial||1||RS-232 on the rear panel|
The board has unpopulated space for two more SDRAMs and a Mini-PCI Type III connector (some supporting parts may be missing).
The board comes with RedBoot custom-tailored to run Clavister's second-stage loader and OS from the CF card.
RedBoot is scattered over a total of 512K of the 4M flash.
|6||IIC SCL||Also on GPIOA1|
|7||IIC SDA||Also on GPIOA1|
|9||PCI INTA||PDC20275 verify me!|
|10||PCI INTB||RTL8100B verify me!|
|12||Rear-panel Reset button (RSW1)||Active low|
connected to switch #RESET pin
also resets the PCI bus
|15||Status LED (LED20)||(probably? Supposed to be the PCI clock?)|
Headers and connectors¶
|2, 4, 6, 8||GND|
Apparently a simplified JTAG header. verify me!
|1, 3, 5, 7||GND|
PS4S1 4-pin Berg- (Mini-Molex-) type power supply connector¶
Of note, there is no +12V.
Console is 9600,8N1.
|Name||FLASH addr||Mem addr||Length||Entry point|
RedBoot comes up with a default menu that allows selecting between booting the Clavister OS (this is done automatically after a timeout) or enter the RedBoot command line.
Although RedBoot is able to write configuration to flash memory, it ignores (at least some of the) settings contained there (console_baud_rate). The flash config doesn't contain the NPE MAC addresses either. Make note of your MAC addresses from the original OS. They may also be printed on stickers on the Ethernet jacks. The bottom sticker also has the MAC address of the WAN port -- add 0x01 for the DMZ MAC, another 0x01 for the LAN MAC.
Booting the Clavister OS is done by the following command sequence:
load -m disk -b 0x100000 hda1:FWLOADER.CFX go -c 0x101028
This will load FWLOADER.CFX from the first CF partition, which must be either FAT (16?) or ext2fs. Any file named FWLOADER.CFX can be loaded as long as it satisfies the following (known) constraints:
- Begins with a 4136-byte long DOS/PE stub (it must be a proper DOS/PE stub, at least to some as-of-yet-unknown extent)
- The payload after the stub must be a tagged image (ie. ELF)
If GPIO5 is grounded when power is applied, the board enters some sort of a simple self-test routine.
RTCK (pin 11) on JB1 (JTAG) is pulled to ground.
There are abundant supplies of ground pins on GPIOA1 and JC1; no need to wrestle with (de-)soldering this pin on JB1 if you have troubles with that.
Two known, EM-436A V1.1 and EM-436A V2.0. The only observable difference between the two are slightly different component use (flash, SDRAMs) and minor differences in the PCB silk.
Annotated board image¶
|1||PS4S1 power connector||11||RTL8100B Ethernet controller|
|2||JP2 Mystery jumper No. 1||12||RTL8305SB Ethernet switch|
|3||JC1 mini-JTAG||13||RS5C372A RTC|
|4||JB1 ARM JTAG||14||SDRAM banks|
|5||GPIOA1 header||15||Mini-PCI Type III connector|
|6||DEBUG2 header||16||IXP422BB SoC|
|7||LED20 Status LED||17||JS28F320 flash|
|8||IMP1 Mystery connector No. 2||18||Compact Flash card|
|9||MAC address stickers||19||RSW1 Reset button|
|10||PDC20275 IDE controller|